Memory Architectures for NoC-Based Real-Time Mixed Criticality Systems
نویسنده
چکیده
Mixed criticality systems (MCS) allow software components of differing criticalities to use the same physical resources (ie. CPU, memory). MCS highlight the trade-off between partitioning components of different criticalities and efficient resource usage. Components are partitioned due to safety concerns, but physical partitioning requires more resources than if components are unpartitioned and share resources. Influential recent work in scheduling of MCS shows the benefits of sharing resources between criticality levels. One issue with this work is that allowing resource sharing within MCS requires that sufficient partitioning and separation can be provided by the architecture to ensure mixed criticality components can share resources without compromising system safety at the highest criticality levels. This paper examines this issue from the perspective of the memory hierarchy for Network-on-Chip architectures, considering memory system design for partitioning to support MCS scheduling approaches for multiprocessor systems – without the need for the resource expensive approaches of totally separated (ie. federated) approaches.
منابع مشابه
GMCB: An Industrial Benchmark for use in Real-Time Mixed-Criticality Networks-on-Chip
This paper specifies and describes GMCB (Generic Mixed-Criticality Benchmark), a benchmark industrial application model for testing real-time mixed-criticality multicore systems incorporating a network-on-chip (NoC). Task execution information such as periods, latencies and criticality levels is specified. The communication patterns between the tasks are defined, incorporating message sizes tra...
متن کاملDesign of a novel congestion-aware communication mechanism for wireless NoC architecture in multicore systems
Hybrid Wireless Network-on-Chip (WNoC) architecture is emerged as a scalable communication structure to mitigate the deficits of traditional NOC architecture for the future Multi-core systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing core...
متن کاملPredictable transactional memory architecture for hierarchical mixed-criticality systems
A transactional memory simplifies the concurrency management in multicore systems by permitting sets of load and store instructions to be executed in an atomic way. The correct results for concurrent transactions and the execution time strongly depend on the coherency potentials, rollback capabilities and strategies of the transactional memory. A transactional memory can be implemented as a Har...
متن کاملBenefits and Implications of the DECOS Encapsulation Approach
In contrast to federated architectures, an integrated architecture provides means to support mixed-criticality systems, i.e., systems that consist of distributed application parts (subsystems) with different criticality levels, on top of the same physical hardware. A major prerequisite for the integration of subsystems with different criticality levels, is given by a strong and reliable protect...
متن کاملReliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)
Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...
متن کامل